The invention relates to a circuit for generating a sampling signal for a UART interface and to a UART interface having such a circuit.
For data transmission between different communication subscribers, what are known as universal asynchronous receiver transmitter (UART) interfaces are frequently used. In a UART receiver, there is typically provision for a data sampling unit designed to take a sampling signal as a basis for sampling a data transmission line. Accordingly, the sampling signal can also be used for sending data. In order to be able to transmit the data between a transmitter and a receiver in as error-free a manner as possible, it is necessary for a frequency of the sampling signal to be adjustable both in the transmitter and in the receiver in as precisely concordant a manner as possible, wherein the frequency of the sampling signal corresponds to a bit rate of the UART interface. To generate the sampling signal, a peripheral clock, for example a processor clock, is frequently divided in a suitable manner. For a given peripheral clock, however, simple dividing of the peripheral clock does not allow arbitrary frequencies of the sampling signal, i.e. bit rates, to be generated.
The invention is based on the object of providing a circuit for generating a sampling signal for a UART interface and a UART interface that allow as precise an adjustment as possible for a frequency of the sampling signal for a given peripheral clock.
The invention achieves this object by way of a circuit for generating a sampling signal for or as part of a UART interface according to the claimed invention, and by a UART interface according to the claimed invention.
The circuit according to the invention is designed to generate a sampling signal for or as part of a UART interface, wherein a frequency of the sampling signal is adjustable and is derived from a peripheral clock.
The circuit has an input terminal to which a peripheral clock, for example a processor clock present in the system, can be applied as intended.
The circuit further has an output terminal at which the sampling signal is output.
The circuit further has a bit rate memory designed to store a value corresponding to a desired bit rate of the UART interface. The desired bit rate or an integer multiple of the bit rate can be stored in the bit rate memory in binary form, for example. In the event of a change in the bit rate, for example triggered by an adjustment process, the value stored in the bit rate memory is altered in accordance with the set bit rate.
The circuit further has a peripheral clock memory designed to store a, for example binary, value corresponding to a frequency of or modeling the peripheral clock.
The circuit further has a sum memory designed to store, for example to store in binary form, a variable sum value.
The circuit further has a computing unit or control unit.
The computing unit is designed to compare a comparison value, which is dependent on the sum value stored in the sum memory (and possibly on further variables), with a threshold value, which is dependent on the value stored in the peripheral clock memory (and possibly on further variables). The computing unit is designed to take the result of the comparing as a basis for generating the sampling signal at a first level or a second level. The first level can be consistent with a logic zero, for example, and the second logic level can be consistent with a logic one, for example. The computing unit is further designed so as, in step with the peripheral clock and on the basis of the result of the comparing, either to alter (to increase or decrease) the sum value stored in the sum memory by the value stored in the bit rate memory or to alter the sum value stored in the sum memory by a value, or to set said sum value to a value, that is dependent on the value stored in the peripheral clock memory.
In one embodiment, the computing unit is designed so as, in step with the peripheral clock, to check whether the comparison value is greater than/equal to or less than the threshold value. If the comparison value is less than the threshold value, the computing unit increases the sum value stored in the sum memory by the value stored in the bit rate memory. If the comparison value is greater than or equal to the threshold value, the computing unit sets the sum value stored in the sum memory to a value consistent with a difference between the comparison value and the threshold value.
In one embodiment, the bit rate memory is designed to store a value consistent with an integer multiple of the desired bit rate of the UART interface, for example 16 times the desired bit rate. If the desired bit rate is 4 Mbit/second, for example, the value stored in the bit rate memory can be 4*16=64, for example.
In one embodiment, the peripheral clock memory is designed to store a value consistent with the frequency of the peripheral clock. If the peripheral clock is 100 MHz, for example, the value stored in the peripheral clock memory can be 100, for example.
In one embodiment, the comparison value is equal to a sum of the sum value stored in the sum memory and the value stored in the bit rate memory.
In one embodiment, the circuit has a summator designed to sum the sum value stored in the sum memory and the value stored in the bit rate memory, and to output the sum at its output terminal as the comparison value. The circuit further has a subtractor designed to form a difference between the value stored in the peripheral clock memory and the sum output by the summator and to output the difference at its output terminal. The circuit further has a comparator designed to compare the value stored in the peripheral clock memory with the comparison value and to take the result of the comparing as a basis for generating the sampling signal at the first or the second level at its output terminal, which is connected to the output terminal of the circuit. The circuit further has a multiplexer that has its control input connected to the output terminal of the comparator, that has its first input connected to the output terminal of the subtractor, that has its second input connected to the output terminal of the summator and that takes the state of the sampling signal as a basis for outputting either the signal present at its first input or the signal present at its second input at its output terminal. The sum memory is in the form of a clock controlled, in particular edge controlled, register, for example in the form of a clock controlled flip-flop, wherein a clock input of the register has the peripheral clock applied to it and an input terminal of the register is connected to the output terminal of the multiplexer.
The invention further relates to a UART interface. The UART interface has at least one data transmission terminal, which is provided for connection to a data transmission line, for example. The UART interface further has a data sampling unit having a sampling control terminal, wherein the data sampling unit is designed to take a sampling signal present at the sampling control terminal as a basis for sampling a signal present at the data transmission terminal. The UART interface further has a circuit as described above, the output terminal of which is connected to the sampling control terminal of the data sampling unit.